Jianhua Gao Presented at APPT 2026
Published:
From July 27–31, 2026, the 17th International Symposium on Advanced Parallel Processing Technology (APPT 2026) was held in Brussels, Belgium. Jianhua Gao from the group attended the conference and gave a presentation titled ARROW: Adaptive Row Reorganization for Warp-Balanced SpMV.
About the Conference
Since its founding in 1995, APPT has become an important international forum for presenting frontier ideas and advancing technology in parallel processing and computing systems. Under the theme Computing Evolved, APPT 2026 focused on next-generation computing paradigms, new hardware and software platforms for computer systems, and the impact of future intelligent technologies on computer architecture; it also highlighted emerging directions in chip design such as domain-specific architectures, agile hardware design methodologies, in-memory computing, and AI chips and chiplet systems.
Presentation Content
Jianhua Gao presented the research work ARROW, which targets Tensor Core acceleration of sparse matrix-vector multiplication (SpMV). SpMV is one of the most important operators in mainstream iterative algorithms such as the Conjugate Gradient (CG) and Generalized Minimal Residual (GMRES) methods, but it is memory-bound, has irregular memory access, and exhibits uneven workloads across rows; moreover, its sparse structure is “mismatched” with the regular, dense Tensor Cores, so a direct mapping incurs substantial padding and redundant accumulation, leading to low GPU utilization. To address these issues, the presentation described three core techniques of ARROW:
Data layout design: reranking rows by the number of nonzeros (NNZ) per row, extracting dense tiles, and generating a new sparse storage format (tcVal, tcColIdx, groupPtr) to reduce the padding ratio.
Register-aware Tensor Core execution: loading matrix tiles into the register layout of the left MMA fragment, gathering and reordering the input vector into the right MMA fragment according to tcColIdx before performing the MMA computation, and sustaining the pipeline via double register buffering.
Load balancing for irregular matrices: using a dedicated kernel for extremely long rows and merging consecutive light rows up to a preset threshold, achieving workload balance at both the block and warp levels.
Highlights
